A power semiconductor device is a semiconductor device usable for causing a large electric current to flow at a high withstand voltage, and is desired to be low in loss. Recently, a power semiconductor device is used for a high rate inverter. For such a use, the semiconductor device is also required to be operable at high speed.
A power semiconductor device is conventionally produced by use of a silicon (Si) substrate. However, recently, a power semiconductor device using a silicon carbide (SiC) substrate attracts attention, and is being developed progressively (see, for example, Patent Documents 1 through 4, etc.).
A breakdown voltage of silicon carbide itself as a material is higher by one digit than that of silicon. Therefore, in the case where a power semiconductor device is produced by use of silicon carbide, even when a depletion layer at a p-n junction or a Schottky junction is thinned, the reverse voltage can be maintained. Accordingly, by decreasing the thickness of the device and increasing the doping concentration of the silicon carbide layer, a power semiconductor device having a low ON resistance, a high withstand voltage and a low loss can be realized. Silicon carbide has a saturated electron velocity which is about twice that of silicon, and therefore can realize a high rate operation.
Hereinafter, a conventional silicon carbide power semiconductor device will be described.
A silicon carbide semiconductor device 1000 shown in FIG. 11 is an n-type planar vertical-type metal-insulator-semiconductor field effect transistor (hereinafter, referred to simply as a “MISFET”). The silicon carbide semiconductor device 1000 includes a semiconductor substrate 101 formed of n+-type SiC. On a main surface of the semiconductor substrate 101, an n−-type first epitaxial layer 120 formed of silicon carbide is provided. In a prescribed region of a surface portion of the first epitaxial layer 120, a p-type body region (well region) 104 having a prescribed depth is provided. A region of the first epitaxial layer 120 other than the body region 104 is a drift region 102. In the vicinity of a surface of the body region 104, an n+-type impurity region (source region) 103 is provided. In the body region 104, a contact region 201 is provided. Generally in order to decrease the contact resistance at a surface of the contact region 201 and in order to decrease the resistance of the contact region 201 itself, the contact region 201 has an impurity profile having a substantially uniform concentration from a surface thereof. Such an impurity profile is referred to as a “box profile”. A second epitaxial layer 105 for connecting the impurity region 103 and the drift region 102 is located so as to cover a surface portion of the body region 104. On a surface of the second epitaxial layer 105, a gate electrode 108 is provided while a gate insulating film 107 is interposed between the second epitaxial layer 105 and the gate electrode 108.
On the surface of the first epitaxial layer 120, an interlayer insulating film 109 is provided so as to cover the gate electrode 108. The interlayer insulating layer 109 has a contact hole for exposing the impurity region 103 and the contact region 201. In the contact hole, a first ohmic electrode (source electrode) 122 is provided, and also a wiring line 110 is provided. A contact hole for exposing the gate electrode 108 is also provided in the interlayer insulating film 109. In this contact hole, a wiring line 112 is provided. Between the wiring line 112 and the gate electrode 108, a metal silicide layer 123 is provided. On a rear surface of the semiconductor substrate 101, a second ohmic electrode (drain electrode) 111 is provided.
In the semiconductor device 1000 shown in FIG. 11, a voltage is applied between the first ohmic electrode 122 and the gate electrode 108 to give an electric field to the gate insulating film 107. As a result, an accumulation type channel 41 is excited in the second epitaxial layer 105, and carriers flow between the first ohmic electrode 122 and the second ohmic electrode 111.
The contact region 201 is formed by, for example, implanting aluminum ion into the first epitaxial layer 120. In silicon carbide, aluminum ion, which is a p-type impurity, is not thermally diffused almost at all. Therefore, the contact region 201 shown in FIG. 11 is formed by a method by which ion implantation is performed a plurality of times at different implantation energy levels, so that the distribution of the impurity concentration in a depth direction is made almost uniform (box profile).
Meanwhile, Patent Document 5 discloses a method by which hydrogen etching or the like is performed after implantation of impurities in order to decrease the contact resistance, so that a peak of the impurity concentration is located in the vicinity of a surface of silicon carbide.